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TSS463B PPAP
TSS463B Serial VAN Data Link Controller ATMEL P/N : TSS463B-TERA
PPAP Submission
Date: Supplier: Address:
2003 October Atmel Nantes SA La Chantrerie BP 70602 44306 NANTES Cedex 3 France Tel : 33(0) 2 40 18 18 18 Fax : 33(0) 2 40 18 19 20
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Rev. 3 : Initial Submission - 2003 October
TSS463B PPAP Table of Contents
1 DESIGN RECORDS .............................................................................................................................................................................. 6 1.1 1.2 2 PRODUCT SPECIFICATION.............................................................................................................................................................6 PACKAGE OUTLINE........................................................................................................................................................................6
ENGINEERING CHANGE DOCUMENTS ................................................................................................................................... 7 2.1 CDC CERTIFICATE OF DESIGN, CONSTRUCTION AND QUALIFICATION............................................................................7 2.1.1 General Product Information................................................................................................................................................... 7 2.1.2 Process Technology Information............................................................................................................................................. 7 2.2 PRODUCT DESIGN...........................................................................................................................................................................8 2.2.1 Product Design Information..................................................................................................................................................... 8 2.2.2 Product Design Validation....................................................................................................................................................... 8 2.2.3 Package Technology Information ........................................................................................................................................... 9 2.2.4 Packing Delivery Information................................................................................................................................................10 2.2.5 Final Test Information ............................................................................................................................................................10 2.2.6 Device Cross Section...............................................................................................................................................................10 2.3 QUALIFICATION AND CHANGE PROCEDURE...........................................................................................................................11 2.3.1 Qualification methodology.....................................................................................................................................................11 2.3.2 Change Procedure...................................................................................................................................................................12 2.3.3 Qualification test methods......................................................................................................................................................13
3 4 5
ENGINEERING APPROVAL..........................................................................................................................................................14 DESIGN FMEA ....................................................................................................................................................................................14 PROCESS FLOW DIAGRAMS .......................................................................................................................................................14 5.1 5.2 5.3 WAFER PROCESSING....................................................................................................................................................................14 ASSEMBLY......................................................................................................................................................................................15 TEST AND PACKING......................................................................................................................................................................15
6 7 8
PROCESS FMEA .................................................................................................................................................................................15 DIMENTIONAL RESULTS .............................................................................................................................................................15 PERFORMANCE TEST RES ULTS ...............................................................................................................................................16 8.1 QUALIFICATION RESULTS ...........................................................................................................................................................16 8.1.1 Wafer Process Qualification..................................................................................................................................................16 8.1.2 Package Qualification.............................................................................................................................................................16 8.1.3 Device Qualification................................................................................................................................................................17 8.1.4 Failure Mechanisms and Corrective Actions......................................................................................................................17 8.1.5 Electrical Distribution in Operating Life-Test....................................................................................................................18 8.1.6 Reliability Calculation............................................................................................................................................................19 8.1.7 ESD Results (HBM) - MIL-STD 883 method 3015.7.........................................................................................................19 8.1.8 Latch-up Results.......................................................................................................................................................................19 8.2 PRODUCT CHARACTERIZATION.................................................................................................................................................19 8.2.1 Characterization environment...............................................................................................................................................19 8.2.2 Corner lot's splits.....................................................................................................................................................................19 8.2.3 Results / Parameter capability...............................................................................................................................................20
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INITIAL PROCESS STUDY ............................................................................................................................................................21
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9.1 10 11 12 13 14 15 16 17 18 19 SCMOS3 PROCESS (Z92G) ........................................................................................................................................................21 MEASUREMENT SYSTEM ANALYSIS STUDY................................................................................................................21 QUALIFIED LABORATORY DOCUMENTATION ..........................................................................................................22 CONTROL PLAN...........................................................................................................................................................................22 PART SUBMISSION WARRANT .............................................................................................................................................23 APPEARANCE APPROVAL REPORT...................................................................................................................................24 BULK MATERIAL REQUIREMENTS ...................................................................................................................................24 SAMPLE PRODUCTION PARTS .............................................................................................................................................24 MASTER SAMPLE........................................................................................................................................................................24 CHECKING AIDS ..........................................................................................................................................................................24 CUSTOMER-SPECIFIC REQUIREMENTS .........................................................................................................................24
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TSS463B PPAP Revision history
Rev 0 1 2 3 Issue 2003 March 2003 June 2003 October 2003 October Modification Notice Initial release (preliminary document) Initial release (revised document) Initial release (revised document) - Add of TSS463B rev 4 reliability assessment Initial release (revised document) - Add of reliability calculation Applicable from 2003 April 2003 June 2003 October 2003 October
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TSS463B PPAP PPAP Checklist
Requirements Table of contents PPAP Checklist 1. Design Records 2. Engineering Change Documents 3. Engineering Approval 4. Design FMEA 5. Process Flow Diagrams 6. Process FMEA 7. Dimensional Results 8. Records of Material / Performance Test Results 8.1 Material Test Records 8.2 Performance Test Records 9. Initial Process Study 10. Measurement System Analysis Study 11. Qualified Laboratory Documentation 12. Control Plan 13. Part Submission Warrant (PSW) 14. Appearance Approval Report 15. Bulk Material Requirements Checklist 16. Sample Production Parts 17. Master Sample 18. Checking Aids 19. Customer Specific Requirements Included yes yes yes yes yes Project risk analysis yes yes Not Applicable Not applicable to IC Yes Yes Yes Yes Yes Yes Not applicable to IC Not applicable to IC To be ordered separately Not attached Not Applicable Not attached
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TSS463B PPAP 1 Design Records
1.1 Product Specification
Please refer to ATMEL's Data Sheet: TSS463B VAN Data Link Controller with serial interface http://www.atmel.com/
1.2
Package Outline
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TSS463B PPAP 2 Engineering Change Documents
2.1 CDC Certificate of Design, Construction and Qualification
2.1.1 General Product Information
Product Name: Function: Wafer Process: Package Type: TSS463B VAN Data Link Controller CMOS 0.5um SO-L.300 16 leads
Locations: Process Development Product Development Wafer Plant QC Responsibility Probe Test Assembly Atmel Nantes , France Atmel Nantes , France Atmel Nantes , France Atmel Nantes, France Atmel Nantes , France ASE Chung Li, Taiwan CHIPPAC, China AMKOR, Korea TSTI Philippines Atmel Nantes, France Global Logistic Center, Philippines Atmel Nantes, France Atmel Nantes, France Atmel Nantes, France
Final Test Lot Release Shipment Control Quality Assurance Reliability Testing Failure Analysis
2.1.2 Process Technology Information
Process Type (Name): Base Material: Wafer Thickness (final) Wafer Diameter Number Of Masks Gate Oxide (Logic transistors) Material Thickness Z92 (SCMOS3 : 0.5um Logic CMOS technology) Bulk silicon 475m 150 mm 14
Silicon Dioxide 110 A
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Polysilicon Number of Layers Thickness Metal Number of Layers Material Layer 1 Thickness Layer 2 Thickness Layer 3 Thickness Passivation Material Thickness 3 AlCu 5150A 5150A 7650A 1 2000A
SiO2 / Nitride 2600A / 6400A
2.2
Product Design
2.2.1 Product Design Information
Die Size Pad Size Opening Logic Effective Channel Length Gate Poly Width (min.) Gate Poly Spacing (min.) Metal 1 Width Metal 1 Spacing Metal 2 Width Metal 2 Spacing Metal 3 Width Metal 3 Spacing Contact size Via 1 size Via 2 size 2200m * 2790 m (6.14mm ) 100m * 100m 0.5m 0.50m 0.60m 0.60m 0.70m 0.80m 0.70m 0.80m 0.70m 0.60m 0.60m 0.60m
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2.2.2 Product Design Validation
Design validation done according to Atmel Nantes development procedure and documented in the following documents: VAN protocol assessment DASSAULT Test Plan Results TSS463B Rev4 ATD-TS-GU-R001 - October 2002 Laurentiu BIRSAN Third Party Application assessment VAN Device TSS463B NSI Test Report DCL-MUX-0077 /V1.0 Jacques TELLIER TSS463B Dynamic Current Analysis APP/LAB/JLL/01/67-0.2 Jean Luc LEVANT
Rev. 3 : Initial Submission - 2003 October
EMC Evaluation
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TSS463B PPAP
2.2.3 Package Technology Information
Package weight Chip separation method Lead frame Material Thickness Size Lead plating Die attach Material Type Wire bonding Material Diameter Method Molding Material Flammability rating Marking Method Drawing example 0.43 g Sawing Cu 10 mils 2 270*270 mils Electroplated Sn/Pb 85/15 Silver epoxy Ablestick 84-1 LMISR4 Au 1.0 mil Thermosonic NITTO MP8000AN UL94V-0 Printed ink (top) and Laser (back) Atmel TSS463B-TERA YYMM Zxxxxxxx
Bonding Diagram
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2.2.4 Packing Delivery Information
Dry packing Tube packed Primary Material Number per unit Secondary Material Number per unit Labeling (minimum) Bar coding Reel packed Primary Material Carrier tape Cover tape Number per unit Secondary Number per unit Labeling (minimum) No Tube Antistatic PVC 36 Box Cardboard 1692 Device type, quantity, Date code, Production code Code 39 to EIA-556-A
Reel Conductive black polystyrene Antistatic film 1500 Box 1 Device type, quantity, Date code, Production code
2.2.5 Final Test Information
Probe equipment Probe temperature Test equipment Test temperature NEXTEST Maverick o 125 C NEXTEST Maverick o o 25 C, 125 C
2.2.6 Device Cross Section
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2.3 Qualification and Change Procedure
2.3.1 Qualification methodology
All product qualifications are split into three distinct steps as shown below. Before a product is released for use, successful qualification testing are required at wafer, device and package level. Wafer Level Reliability consists in testing individually basic process modules regarding their well known potential limitations (Electromigration, Hot Carriers Injection, Oxide Breakdown, NVM Data Retention). Each test is performed using a dedicated wafer process structure. Device reliability is covering either dice design and processing aspects. The tests are performed on device under qualification, and generic data may also be considered for reliability calculation. For each package type proposed in the Datasheet, it is verified that qualification data are available. If not qualification tests are carried out for the new package types. At least one package type is selected to verify packaging reliability of the devi ce under qualification.
Product Qualification
Wafer Level
Device (Design / Process)
Packaging
Reliability
Reliability
Reliability
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2.3.2 Change Procedure
All changes are controlled by ECN (Engineering Change Notice). Major changes are notified to customers using products affected by the change. Major changes are defined as changes which may affect the electrical and/or mechanical product specification. The following checklist provides the minimum list of items to be considered.
1 1-1 1-2 1-3 1-4 1-5 1-6 2 2-1 2-2 2-3 2-4 2-5 3 3-1 3-2 3-3 3-4 3-5 4 4-1 4-2 4-2 4-3
General Changes Manufacturing line Sequence of fabrication process cycle Material type Electrical parameter External physical dimension Die size Changes Specific to Wafer Fabrication Doping method Gate oxide formation method Equipment change Layer Thickness Module dimensions Changes Specific to Asse mbly Sawing method Die attach method Wiring method Molding process Lead finish / MSL classification Changes Specific to Test Specification limit Test coverage reduction Product identification Final conditioning
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2.3.3 Qualification test methods
General Requirements for Plastic Encapsulated CMOS Ics. Standard MIL-STD 883 Method 1005 MIL-STD 883 Method 1005 MIL-STD 883 Method 3015.7 JEDEC 78 Test Description Electrical Life Test (Early Failure Rate) 48 hours 140C Electrical Life Test (Latent Failure Rate) 1000 hours 140C Dynamic or Static Electrostatic Discharge HBM +/-2000v 1.5kOhm/100pF/3 pulses Latch up 50mW power injection, 50% overvoltage @125C NVM Endurance Program Erase Cycles 125C NVM Data Retention High Temperature Storage 165C Temperature Cycling 1000 cycles -65C/150C air/air Autoclave 96 hours 130C/85%RH 85/85 Humidity Test 1000 hours 85C/85%RH HAST 96 hours 130C/85%RH/biased Preconditioning Soldering Stress 220C/235c/3 times Solderability Acceptance 0/800 - 48h
0/77 - 1000h
0/3 per level
0/5 per stress
AEC Q100 Method 005 AEC Q100 Method 005 MIL-STD 883 Method 1010 EIA JESD22-A110 EIA JESD22-A101 EIA JESD22-A110 EIA JESD20 MIL-STD 883 Method 2003 MIL-STD 883 Method 2015
0/77 - 100kc
0/77 - 1000h
0/77 - 500c
0/77 - 96h
0/77 - 1000h
0/50 - 96h
0/11 per class
0/3
Marking Permanency
0/5
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TSS463B PPAP 3 Engineering Approval
TSS463B is qualified since 2003 March Released to production review was done in 2003 May Release to Production is approved by: O O O O O O O O Head of Technical Center Project Leader Product Engineering Operation Back-end Operation Front-end Quality Management Marketing Business Planning
4 Design FMEA
Project Risk Analysis has been initiated at Feasibility stage and followed under Project Leader responsibility, all over project development stages. Project Risk Analysis report may be consulted in Atmel Nantes upon request.
5 Process Flow Diagrams
5.1 Wafer Processing
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17.
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Incoming inspection of silicon wafers Locos (Z92) Isolation MOS N-Well implants and N Well diffusion MOS P-Well Implants MOS Gate oxidation Polysilicon deposition and MOS gate definition MOS Implants with Spacer definition Salicide Hard mask definition Salicide module ILD deposition and SOG planarization Contact etching and Plug1 filling Metal 1 deposition and etching IMD1 and REB planarization Via1 etching and Plug2 filling Metal 2 deposition and etching IMD2 and REB planarization Via2 etching and Plug3 filling
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TSS463B PPAP
18. 19. 20. 21. 22. Metal 3 deposition and etching Passivation deposition and Pad etching E-Test Back grinding Wafer sort
5.2
Assembly
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Wafer mount Wafer saw First optical Die bonding Wire bonding Molding Solder plating Top marking Trim and form Final visual inspection
5.3
1. 2. 3.
Test and Packing
Room temperature initial test Final quality checks Packing
6 Process FMEA
Process FMEA for 0.5um Z92 may be consulted in Atmel Nantes upon request.
7 Dimentional Results
SO-L.300 16 leads package comply with JEDEC standard outline. Package dimensions were checked during Package Qualification.
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TSS463B PPAP 8 Performance Test Results
8.1 Qualification Results
8.1.1 Wafer Process Qualification
ATMEL 0.5m SCMOS3 wafer process is qualified since 1997, September.
8.1.2 Package Qualification
Package qualification measurements carried out on VAN DLC devices are detailed in the table below: Lots Z40807C Device Type TSS463B SO-L.300 16 AMKOR K Test Description 85/85 Humidity Thermal Cycles Step 500h 1000h 500c Result Comment 0/77 0/77 0/77 0/5 0/5 0/72 0/77 0/77 0/77 0/11 0/231 0/50 0/50 0/50 0/72 0/77 0/50 0/50 0/11 0/231 0/77 0/77 0/77 0/77 0/77 0/11 0/231 0/77 0/77 Post preconditioning level1 Post preconditioning level1 Ball shear cpk:1.70 (30 pads) Wire pull cpk:2.35 (30 wires) Post preconditioning level1
Z41393J
TSS461E SO-L.300 24 AMKOR K
HAST after Thermal Shocks High Temperature Storage 165C Moisture sensitivity JESD20 - level1 85/85 Humidity Thermal Cycles HAST after Thermal Shocks High Temperature Storage 165C Moisture sensitivity JESD20 - level1 85/85 Humidity Thermal Cycles HAST after Thermal Shocks Moisture sensitivity JESD20 - level1 High Temperature Storage 165C
1000c 96h 500h 1000h CSAM Elect 500h 1000h 500c 1000c 96h 500h 1000h CSAM Elect 500h 1000h 500c 1000c 96h CSAM Elect 500h 1000h
Post preconditioning level1 Post preconditioning level1 Post preconditioning level1
Z45925A (Note 1)
TSS463B rev4 SO-L.300 16 ASE CL
Post preconditioning level1 Post preconditioning level1 WP-Cpk= 1.67, BS-Cpk=1.89 Post preconditioning level1
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Additional assembly qualification reports are available under the following references: ASE Chung Li : QR0813 (2002/09/23) CHIPPAC China : QR0726 (2002/05/13)
8.1.3 Device Qualification
Device qualification is based upon HTOL results of 3 lots as detailed in the table below: Lot Z40807C Device Type TSS463B SO-L.300 16 AMKOR K TSS461E SO-L.300 24 AMKOR K TSS463B rev4 SO-L.300 16 ASE CL Test Description EFR Dynamic Life Test 140c/5.75v LFR Life Test 140c/5.75v EFR Dynamic Life Test 140c/5.75v LFR Life Test 140c/5.75v EFR Dynamic Life Test 140c/5.75v LFR Life Test 140c/5.75v Step 48h 500h 1000h 48h 500h 1000h 48h 500h 1000h Result 0/774 0/77 0/77 0/795 0/77 0/77 0/800 0/100 0/100 Comment
Z41393J
Z45925A (Note 1)
Note 1: In this revision of the TSS463B PPAP, are reported the reliability results of the final production version of the circuit (Rev 4 design). The measurements have been carried out on lot Z45925A DC0327.
8.1.4 Failure Mechanisms and Corrective Actions
No failure mechanism reported in this document. The table here below presents additional Reliability Monitor Data performed during the first quarter of 2003. Lot Z44574F Device Type TSSIO16E SO-L.300 28 AMKOR K Test Description EFR Dynamic Life Test 140c/5.75v LFR Life Test 140c/5.75v Moisture sensitivity JESD20 - level1 85/85 Humidity Thermal Cycles Autoclave post Thermal Shocks Step 48h 500h 1000h CSAM Elect 500h 1000h 500c 1000c 96h Result 0/300 0/77 0/77 0/11 0/150 0/50 0/50 0/50 0/50 Comment
Post preconditioning level1 (Test in progress) Post preconditioning level1 Post preconditioning level1
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8.1.5 Electrical Distribution in Operating Life-Test
In order to assess the drift of product performance under HTOL stress 30 parts have been submitted to 1000 hours 140c/5.75v aging. All specified AC and DC Parameters have been recorded prior (initial) and post stress (final) for the lot Z41521. The table below summarizes the results with total drift ratio and final Cpk. No significant drift noticed after HTOL aging. Final Cpk values are higher than 1.33. HTOL performance records for the rev 4 design (lot Z45925A) have been included in the table as well. The records do not indicate any change in the performance of the circuit.
Symbol ICCSB ICCOP VIL CMOS VIL1 VIH CMOS VIH1 VOL TXD VOL INTB VOH TXD IIL RESET TCYC TW SCKH TW SCKL TSU TH TV
Parameter Static Consumption Active Consumption Input Low Level XTAL 1 Low Level Input High Level XTAL 1 In High Level TXD Out Low Level INTB Out Low Level TXD Out High Level RESET Low Leakage Cycle Time SPI Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable to Data Valid
Specification Vcc (*) 50uA max 9 mA max 1.5V min 1.5V min 3.5V max 3.5V max 0.4V max 0.4V max 2.4V min 78.5uA max 250ns max 100ns max 100ns max 40ns max 40ns max 60ns max 5.5V 5.5V 4.5V 4.5V 5.5V 5.5V 4.5V 4.5V 4.5V 5.5V 4.5V 4.5V 4.5V 4.5V 5.5V 4.5V
Typical 0.050 2.20 1.51 1.66 3.16 3.15 0.22 0.22 4.1 20.6 9.3 3.41 5.9 0.80 -0.52 30.1
Initial 0.049 2.23 1.51 1.70 3.12 3.11 0.21 0.21 4.0 21.3 9.3 3.41 5.9 0.80 -0.52 32.6
Final 0.046 2.25 1.54 1.69 3.23 3.21 0.23 0.23 4.0 22.6 9.4 3.47 5.9 0.86 .052 31.5
Drift (%) -6.1 0.9 2.0 0.6 3.5 3.2 9.5 9.5 0.0 6.1 1.1 1.8 0.0 7.5 0.0 -3.4
Cpk >20 >20 1.6 3.4 1.5 1.6 10.2 9.3 3.7 >20 >20 >20 >20 >20 >20 7.5
Z45925A 0.051 2.24 1.63 1.70 3.11 3.10 0.23 0.24 4.0 20.8 9.3 3.41 5.9 0.79 -0.52 31.6
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8.1.6 Reliability Calculation
Reliability calculation requires a large base of measurement data in prospect of targeting the objectives of Automotive Market. Therefore the data source is enlarged to 2003 records of digital 0.5um Nantes products. Sample size Early Life Failures Latent Failures 1.9E6 2880E3 Failures 7 0 Failure Rate 4 2 Projected Failure Rate 3 1 Unit PPM FIT
8.1.7 ESD Results (HBM) - MIL-STD 883 method 3015.7
Lot Z40807C Device Type TSS463B SO-L.300 16 AMKOR K Test Description ESD HBM Step 2000v 3000v 4000v Result 0/3 0/3 0/3 Comment Class 3 of MIL STD 883 Method 3015 (ESD0113)
8.1.8 Latch-up Results
Lot Z40807C Device Type TSS463B SO-L.300 16 AMKOR K Test Description LATCH-UP Power Injection Over voltage Step Result Comment
50mw 10v
0/5 0/5
Latch-up free (min value: 180mW at 125c)
8.2
Product Characterization
8.2.1 Characterization environment
Tester: Lot: Process: Perso Code: Assy package: Sentry 15 Z43525 Z92 0RD7 (design Rev 4) TE (SO-L.300 16 leads)
8.2.2 Corner lot's splits
In order to characterize the product with the maximum excursion of the process, corner run splits have been manufactured using :
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Variations on LeffP and LeffN Variations on VTP and VTN
The sample size is 3 parts per corner plus 6 parts in the group of typical values (Total 21 parts).
8.2.3 Results / Parameter capability
All specified AC and DC Parameters have been characterized for Rev 4 design version. They present Cpk values higher than 1.6. The comparison of Rev 1 and Rev 4 characteristics does not point out any difference. Characterization results have been submitted to a detailed customer review (TSS463B Test Review) held in Nantes on 27/11/2001. The next table provides the main product characteristics based upon Mask 6046 Rev 4 evaluation results. All TSS463B AC parameters are reported in this table. Symbol ICCSB ICCOP VIL CMOS VIL1 VIH CMOS VIH1 VOL TXD VOL INTB VOH TXD IIL RESET TCYC TW SCKH TW SCKL TSU TH TV Parameter Static Consumption Active Consumption Input Low Level XTAL 1 Low Level Input High Level XTAL 1 In High Level TXD Out Low Level INTB Out Low Level TXD Out High Level RESET Low Leakage Cycle Time SPI Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable to Data Valid Specification (1) 50uA max 9 mA max 1.5V min 1.5V min 3.5V max 3.5V max 0.4V max 0.4V max 2.4V min 78.5uA max 250ns max 100ns max 100ns max 40ns max 40ns max 60ns max Vcc (*) 5.5V 5.5V 4.5V 4.5V 5.5V 5.5V 4.5V 4.5V 4.5V 5.5V 4.5V 4.5V 4.5V 4.5V 5.5V 4.5V Temp (*) 125 -40 -40 -40 -40 -40 125 125 125 -40 125 125 125 125 -40 125 Average 2.9uA 2.7mA 1,6V 1,7V 3.2V 3.2V 0.22V 0.23V 3.9V 26.5uA 10ns 5.5ns 5.9ns 0.8ns -0.5ns 36.7ns Cpk 9.6 > 20 1.61 4.0 5.7 4.7 18.0 12.3 > 20 > 20 > 20 14.7 >20 >20 >20 14.1
(*) worst case condition
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TSS463B PPAP 9 Initial Process Study
9.1 SCMOS3 process (Z92G)
Parameters controlled during Electrical Test : NMOS/PMOS :junction Breakdown Voltage, Threshold voltage, electrical width & length, Thin oxide Breakdown Voltage, Sub-threshold current. Sheet Resistance : N+, P+, WELL, PolyN, PolyP, Unsalicided Poly Metal continuity / isolation: metal1, metal2, metal3 Contacts/ Vias1 & Vias2 resistance Contacts Breakdown Voltage Salicide isolation Cpk history (Last update 23/01/2003) :
Z92G Cpk distribution
120%
100%
80%
Repartition (%)
60%
40%
20%
0% 02/01 Cpk<1.33 (%) Cpk>=1.33 & <1.66 (%) Cpk>=1.66 (%) 5% 5% 89% 02/02 3% 5% 92% 02/03 5% 3% 92% 02/04 8% 5% 86% 02/05 5% 19% 76% 02/06 5% 5% 89% 02/07 8% 11% 81% Mois 02/08 0% 3% 97% 02/09 8% 5% 86% 02/10 14% 0% 86% 02/11 0% 3% 97% 02/12 3% 5% 92% 03/01 3% 3% 95%
Cpk<1.33 (%)
Cpk>=1.33 & <1.66 (%)
Cpk>=1.66 (%)
Lineaire (Cpk<1.33 (%))
Lineaire (Cpk>=1.66 (%))
10 Measurement System Analysis Study
Repeatability and Reproducibility tests are performed on all the manufacturing equipments. Critical parameters and equipments are followed under SPC system. In addition Equipment performance is assessed by GRR and through regular maintenance activity.
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TSS463B PPAP 11 Qualified Laboratory Documentation
Internal Lab - COMPLIANT QS-9000 3rd edition
Application Lab Calibration Lab Characterization Lab Chemical Lab Scope Check the functionality of products to customer applications Standard Gage Calibration Product and process characterization before completing industrialization Incoming inspection on chemical products and process monitoring on DI water , gases Product Reliability Testing Failure Analysis and Yield enhancement
Environmental Lab Technology Analysis Lab
12 Control Plan
Control plan is composed of the following: Wafer fab Control Plan for Z92G process Assembly Control Plan Test Control Plan
Front-end and Back-end operation control plans may be consulted in Atmel Nantes upon request. Test Control Plan:
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TSS463B PPAP 13 Part Submission Warrant
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TSS463B PPAP 14 Appearance Approval Report
Not Applicable for IC
15 Bulk Material Requirements
Not Applicable for IC
16 Sample Production Parts
Not attached, delivered previously
17 Master Sample
Not attached.
18 Checking Aids
Not applicable
19 Customer-Specific Requirements
Not attached.
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Rev. 3 : Initial Submission - 2003 October

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